In recent years, the bandwidth required for inter-chip data transmission has been rapidly expanding. To cope with the situation, serial transmission systems which are not affected by skews between signal lines have come to be widely used instead of parallel transmission systems which have been in use to transmit plural pieces of data and clock signals concurrently. In a serial transmission system, data with embedded clock signals is transmitted via a single signal line to be recovered into the data and clock signals by a CDR circuit on a receiving side.
FIG. 10 schematically shows the configuration of a CDR circuit 1000 including a track-and-hold type phase detector as disclosed in reference literature: A. Pottbacker, et al. “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s” (IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp 1747-1751, 1992). A symbol determination unit 1001 determines the symbol of an input data signal DIN 102 in synchronization with a recovered clock signal CLK 103 recovered by a voltage-controlled oscillator (VCO) 1005 and outputs recovered data DOUT 1002. A phase detector circuit 101 compares the phases of the recovered clock signal CLK and the input data signal DIN, and outputs a phase difference signal 104 representing the phase difference between them. A low-pass filter 1003 temporally averages the phase difference signal 104 and outputs an oscillation frequency control voltage 1004 to the VCO. Namely, when the recovered clock signal CLK is, on the average, behind the input data signal DIN in phase, the oscillation frequency of the VCO is increased; and, when the recovered clock signal CLK is, on the average, ahead of the input data signal DIN in phase, the oscillation frequency of the VCO is decreased. This aligns the recovered clock signal CLK and the input data signal DIN in phase allowing the symbol determination unit 1001 to correctly determine the symbol of the input data signal DIN.
FIG. 11A schematically shows an example configuration of a principal portion of the track-and-hold type phase detector circuit 101 shown in FIG. 10. FIG. 11B is a timing chart of an example operation of the track-and-hold type phase detector circuit. Referring to FIG. 11A, the track-and-hold type phase detector circuit 101 includes a track-and-hold circuit 1101. The track-and-hold circuit 1101 tracks and holds the recovered clock signal CLK in synchronization with a rising edge of the input data signal DIN, and outputs it as a phase difference signal. The recovered clock signal CLK is, as shown in FIG. 11B, formed of a voltage waveform with limited rising/falling time. Therefore, tracking and holding the recovered clock signal CLK in synchronization with a rising edge of the input data signal DIN causes the phase difference between the input data signal DIN and the recovered clock signal CLK to be converted into voltage and then outputted. Even though, in the configuration of the track-and-hold circuit shown in FIG. 11A, the track-and-hold circuit operates only in synchronization with a rising edge of the input data signal DIN, there are many cases where an additional track-and-hold circuit which operates in synchronization with a falling edge of the input data signal DIN is also used so as to perform phase comparison between the input data signal DIN and the recovered clock signal CLK at both rising and falling edges of the input data signal DIN.
A CDR circuit can be formed in a half-rate architecture or a 1/N rate architecture. In a half-rate architecture, the clock signal CLK has a frequency equaling one half of a symbol rate and the input data signal DIN is checked in synchronization with a rising edge and also in synchronization with a falling edge of the clock signal CLK. In a 1/N rate architecture, N-phase clock signals are used with each clock signal having a frequency equaling 1/N times a symbol rate. FIG. 12 is a timing chart of operation in a half-rate architecture of the track-and-hold type phase detector circuit, shown in FIGS. 11A and 11B, disclosed in the above reference literature. Since the clock signal CLK has a frequency equaling one half of the symbol rate of the input data signal DIN, the output voltage is either high or low depending on with which one of a rising edge and a falling edge of the clock signal CLK a rising edge of the input data signal DIN is synchronized. Namely, when the track-and-hold type phase detector circuit disclosed in the above reference literature and described above with reference to FIGS. 11A and 11B is used in a half-rate architecture, it may output two, i.e. high and low, phase difference signals even with the phase difference between the input data signal DIN and the clock signal CLK unchanged. This makes the phase detector circuit useless.
FIG. 13 is a block diagram of an example configuration of the track-and-hold type phase detector circuit, which is compatible with a half-rate architecture, disclosed in JP-A No. 2007-267005 to cope with the above problem. The track-and-hold type phase detector circuit shown in FIG. 13 includes, in addition to a track-and-hold circuit 1101, a determination circuit 1301 and a polarity inversion circuit 1302. The determination circuit 1301 determines with which of a rising edge and a falling edge of the clock signal CLK a rising edge of the input data signal DIN is synchronized. When the rising edge of the input data signal DIN is synchronized with a rising edge of the clock signal CLK, the polarity inversion circuit 1302 outputs the signal received from the track-and-hold circuit 1101 as it is as a phase difference signal 104. When the rising edge of the input data signal DIN is synchronized with a falling edge of the clock signal CLK, the polarity inversion circuit 1302 outputs the signal received from the track-and-hold circuit 1101 as a phase difference signal 104 after inverting its polarity. This allows the phase detector circuit 101 in a half-rate architecture to output a correct phase difference signal regardless of whether the rising edge of the input data signal DIN is synchronized with a rising edge or a falling edge of the clock signal CLK.
The track-and-hold type phase detector circuit compatible with a half-rate architecture disclosed in JP-A No. 2007-267005 and shown in FIG. 13 may be used in a CDR circuit included in a serializer/deserializer which performs, in a data communication device, conversion between a relatively low-speed, higher-layer digital signal and a high-speed serial signal (analog waveform).